In an optical access market, optical transceivers are used. As an optical transceiver, the micro-optics type module and the PLC (Planar Lightwave Circuit) module are known. The micro-optics type module includes an LD (Laser Diode), a PD (Photodiode), a thin film filter, a lens, and the like. The PLC module is configured by fabricating a quartz waveguide on a silicon substrate, and surface-mounting an LD, PD and the like. Both of them have advantages and disadvantages; however, the PLC module is advantageous in cost and delivery because it is not required to perform the optical axis adjustment while monitoring the optical output.
As a mounting method for such a PLC module, the passive alignment mounting is known. In the passive alignment mounting, alignment of a waveguide chip in the planar direction is performed by image-recognizing alignment markers with infrared light. Alignment in the vertical direction is performed with a block called the pedestal. The pedestal is fabricated with high accuracy. By putting an optical part on the pedestal, the height of the optical part and the height of an optical waveguide can be aligned with high accuracy.
FIG. 1 is a birds-eye view illustrating a reference example of the passive alignment mounting. FIG. 2A is a plan view and FIG. 2B is a side view. In this reference example, a semiconductor laser chip (LD chip) is presumed as an optical element. An optical circuit part 120 is formed on a silicon substrate 101. The optical circuit part 120 is formed with a core 105 functioning as an optical waveguide.
The optical circuit part 120 can be formed by a following method: on the silicon substrate 101, a lower clad layer 102 is formed. On the lower clad layer 102, a core layer serving as a source of the core 105 is formed. On the core layer, a photoresist having a pattern of the core 105 is formed by the photolithography technique. An unmasked portion is removed by the RIE (Reactive Ion Etching), and thereby the core 105 is formed. Subsequently, a reflow glass layer 103 (or a buried layer) is formed. On the reflow glass layer 103, an upper clad layer 104 is formed to thereby complete the optical circuit part 120.
Examples of a cross-sectional configuration of the optical circuit part 120 formed by such a process are illustrated in FIGS. 3 and 4. If the thickness of the film removed by the RIE is small, an unnecessary core layer 105a remains in addition to an optical waveguide region as illustrated in FIG. 4. In such a configuration, optical waveguide characteristics are largely deteriorated, and therefore it is not preferable that the unnecessary core layer 105a remains.
In order to surely remove the unnecessary core layer 105a, the lower clad layer 102 is typically also etched to some portion thereof in the core layer etching step because it is impossible to selectively etch only the core layer by the RIE. FIG. 3 illustrates a cross-sectional structure of the optical circuit part 120 formed in this manner. In this example, a lower surface of the core 105 is higher than the boundary face between the lower clad layer 102 and the reflow glass layer 103 in a region other than the core 105. FIG. 1 illustrates such a stacked structure.
In order to mount the LD chip 109, a silica film in a predetermined region on the silicon substrate 101 is removed. On the silicon substrate 101 in that region, pedestals 106, an electrode 107, and alignment markers 108 are formed. The pedestals 106 are designed such that when the LD chip 109 is placed on the pedestals 106, the height of an active layer 110 of the LD chip 109 and the height of the core 105 of the optical circuit part 120 coincide with each other. The electrode 107 is formed to make an electrical connection to a connecting terminal of the LD chip 109. By aligning the alignment markers 108 with alignment markers 115 on an LD chip 109 side, and fixing the LD chip 109 to the pedestals 6, an optical axis in the planar direction can be aligned.
The followings are reference techniques regarding the connection between an optical waveguide formed on a substrate and an optical element: Japanese Laid-Open Patent Application JP-A-Showa, 63-5310; and Japanese Laid-Open Patent Application JP-A-Heisei, 8-334655.